The present invention relates to a frequency synthesizer and, more particularly, to a fractional-N-PLL frequency synthesizer and a phase error canceling method therefor.
Recent mobile communication devices use a fractional division (fractional-N) frequency synthesizer that has an excellent fast channel switching capability. As shown in FIG. 1, the fractional-N PLL frequency synthesizer 50 includes a phase comparator 51, a charge pump 52, a low-pass filter (LPF) 53, a voltage controlled oscillator (VCO) 54, a variable frequency divider 55a and an accumulator 55b. 
The phase comparator 51 compares the phase of a reference signal fr with the phase of a comparison signal fp and provides the resulting phase difference signals "PHgr"R and "PHgr"P to the charge pump 52. The charge pump 52 generates a voltage signal Do according to the phase difference signals "PHgr"R and "PHgr"P and provides the voltage signal Do to the LPF 53. The LPF 53 smoothes the voltage signal Do from the charge pump 52 and provides the VCO 54 with a control voltage signal from which a high-frequency component has been removed.
The VCO 54 generates a frequency signal fvco according to the voltage value of the control voltage signal and provides the frequency signal fvco to the variable frequency divider 55a. The variable frequency divider 55a frequency-divides the frequency signal fvco while changing the frequency dividing ratio from M division to M+1 division every time an overflow signal OVF is supplied from the accumulator 55b, and provides the comparison signal fp to the phase comparator 51.
The fractional-N-PLL frequency synthesizer 50 is able to change the frequency signal fvco in finer steps than the reference signal fr. However, since the fractional-N-PLL frequency synthesizer 50 performs fractional division (averaging of a frequency divided value) in an equivalent manner, a phase error is generated. FIG. 2 is a timing chart of the reference signal fr and the comparison signal fp. In this example, the fractional-N-PLL frequency synthesizer performs frequency division of 1/8 and is locked. The reference signal fr is 200 kHz and the frequency signal fvco is 800.025 MHz.
Even in the locked state, as apparent in FIG. 2, phase errors xcex94t0 to xcex94t7 are generated between the reference signal fr and the comparison signal fp in a cycle of 25 kHz. Specifically, suppose that the phase error xcex94t0 between the reference signal fr and comparison signal fp whose phases match with each other is 0.000 nanoseconds (ns). The first phase error xcex94t1 between the following reference signal fr and comparison signal fp is 1.094 ns, the second phase error xcex94t2 between thereafter reference signal fr and comparison signal fp is 0.938 ns, the third phase error xcex94t3 between thereafter reference signal fr and comparison signal fp is 0.782 ns, the fourth phase error xcex94t4 between thereafter reference signal fr and comparison signal fp is 0.626 ns, the fifth phase error xcex94t5 between thereafter reference signal fr and comparison signal fp is 0.470 ns, the sixth phase error xcex94t6 between thereafter reference signal fr and comparison signal fp is 0.314 ns, and the seventh phase error xcex94t7 between thereafter reference signal fr and comparison signal fp is 0.158 ns. Then, the phases of the next reference signal fr and comparison signal fp match with each other, so that the phase error xcex94t0 returns to 0.000 ns. Thereafter, the phase errors xcex94t0 to xcex94t7 are cyclically generated between the reference signal fr and the comparison signal fp.
When the fractional-N-PLL frequency synthesizer 50 is locked, the phase errors xcex94t0 to xcex94t7 cause the pulse widths of the phase difference signals "PHgr"P and "PHgr"R provided to the charge pump 52 by the phase comparator 51 to be different from each other. As a result, even if the charge pump 52 is locked, the voltage signal Do varies. The variation in the voltage signal Do cannot be canceled by the LPF 53 that has a relatively small time constant. Therefore, the spurious level of the frequency signal fvco output from the VCO 54 falls. That is, the phase errors xcex94t0-xcex94t7 that are cyclically generated increase the spurious.
To suppress the spurious, the fractional-N-PLL frequency synthesizer 50 has a spurious cancel circuit 56 as shown in FIG. 1. The spurious cancel circuit 56 generates a cancel signal that has a phase opposite of that of the voltage signal Do, the latter varies with the phase errors xcex94t0-xcex94t7. More specifically, a digital-analog converter (not shown) of the spurious cancel circuit 56 receives a digital signal acquired by scaling the phase errors xcex94t0-xcex94t7 from the accumulator 55b and generates the cancel signal by performing a digital-analog conversion on the digital signal. The reason for using the digital signal of the accumulator 55b is that the digital signal is proportional to the phase errors xcex94t0-xcex94t7.
A variation in the voltage signal Do is canceled by superimposing the cancel signal from the spurious cancel circuit 56 onto the voltage signal Do. The variation-canceled voltage signal Do is then supplied to the VCO 54 via the LPF 53. As such, even if the phase errors xcex94t0 to xcex94t7 are generated cyclically, a spurious-reduced frequency signal fvco is output from the VCO 54.
However, since the spurious cancel circuit 56 has a digital-analog converter and an analog circuit, it is dependent upon the supply voltage and the temperature. Therefore, the spurious cancel circuit 56 is susceptible to variations in the supply voltage and temperature, and hence unable to generate a cancel signal that effectively reduces the spurious.
Further, the digital-analog converter and the analog circuit of the spurious cancel circuit 56 inevitably increase the circuit area and power consumption of the system.
Accordingly, it is an object of the present invention to provide a fractional-N-PLL frequency synthesizer that reduces the spurious caused by a phase error when it is locked.
In a first aspect of the present invention, a method of canceling a plurality of phase errors generated between a reference signal and a comparison signal when a fractional-NPLL frequency synthesizer is locked is provided. First, a reference phase error is determined from the plurality of phase errors. Then, any phase error equal to or smaller than the reference phase error is canceled.
In a second aspect of the present invention, an alternative method of canceling a plurality of phase errors generated between a reference signal and a comparison signal when a fractional-N-PLL frequency synthesizer is locked is provided. First, a reference phase error is determined from the plurality of phase errors. Second, a plurality of phase difference signals are generated according to the phase errors equal to or smaller than the reference phase error, wherein each phase difference signal has a pulse waveform. Third, any phase error equal to or smaller than the reference phase error is canceled by canceling the pulse waveforms of the plurality of phase difference signals.
In a third aspect of the present invention, a fractional-N-PLL frequency synthesizer is provided. The synthesizer includes a phase comparator for generating a phase difference signal by comparing a reference signal with a comparison signal, and a charge pump for receiving the phase difference signal from the phase comparator and converting the phase difference signal into a voltage signal. A low-pass filter is connected to the charge pump to smooth the voltage signal so as to generate a voltage control signal. A voltage controlled oscillator is connected to the low-pass filter to generate a frequency signal having a frequency according to the voltage control signal. A variable frequency divider is connected to the voltage controlled oscillator to frequency-divide the frequency signal to generate the comparison signal. A plurality of phase errors including a predetermined reference phase error are generated between the reference signal and the comparison signal when the fractional-N-PLL frequency synthesizer is locked. A canceling circuit is connected to the variable frequency divider to cancel any phase error equal to or smaller than the predetermined reference phase error.
In a fourth aspect of the present invention, an alternative fractional-N-PLL frequency synthesizer is provided. The synthesizer includes a first phase comparator for generating a first phase difference signal by comparing a reference signal with a comparison signal, and a charge pump for receiving the first phase difference signal from the phase comparator and converting the first phase difference signal into a voltage signal. A low-pass filter is connected to the charge pump to smooth the voltage signal to generate a voltage control signal. A voltage controlled oscillator is connected to the low-pass filter to generate a frequency signal having a frequency according to the voltage control signal. A variable frequency divider is connected to the voltage controlled oscillator to frequency-divide the frequency signal, so to generate the comparison signal. A plurality of phase errors including a predetermined reference phase error are generated between the reference signal and the comparison signal when the fractional-N-PLL frequency synthesizer is locked. A selection circuit is connected to the variable frequency divider and the first phase comparator to distribute a first set of a reference signal and a comparison signal having no phase error therebetween, and a second set of a reference signal and a comparison signal having a phase error equal to or smaller than the predetermined reference phase error therebetween. The first set of reference and comparison signals is provided to the first phase comparator. A second phase comparator is connected to the selection circuit to receive the second set of reference and comparison signals and generate a second phase difference signal having a pulse waveform. A filter circuit is connected to the second phase comparator and the charge pump to delete the pulse waveform of the second phase difference signal and provide the pulse-waveform-deleted second phase difference signal to the charge pump.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.